• Description of Importance of Technology to DOW / Dual Use

Year 2 Efforts

1. Full electrical datasheet from 3.3kV fabricated device at GE Aerospace

2. DMOS Automated Tools for CAD creation, profiling and Checking

• GE Aerospace have developed, 3 tools to aid in the creation and testing of power MOSFET device CAD.
  • Parameterized DMOS device generation. This tool allows full freedom in editing a device’s geometric constraints to yield a termination and active area layout to match desired performance characteristics
  • 2D Cross-Section layer stack-up. This tool allows an arbitrary 2-dimensional simulated view of any section of a DMOS layout to see how the layer stack-up might look after processing.
  • DRC automated checking. This tool allows the selection of which DRC tests to run on a given library and will generate an annotated GDS library showing any violations
• All three of these tools are developed using a combination of KLayout and Python, both of which are open-source and freely available. Each is intended to reduce time investment and errors and add flexibility to device variation design by eliminating much of the time needed for customization.

3. Expanded Offering on Unit-Process Modules both for 100mm and 150mm substrates.

• A flowchart for fabrication of SiC MOSFET is presented below. GE currently provide services with flexibility on partial processes that include implantation masking, activation anneal and rapid thermal processing for ohmic contact modules.

EDA Description

3.3kV EDA offering include a representative SPROCESS and SDEVICE models for both 3.3kV FETs, TCAD-based parameterized cell-level SPICE models for both voltage nodes (MYSTIC); Calibrated SPICE models using fabricated devices; Identify geometrical and process variability parameters to offer flexibility to users and final parameterized cell-level SPICE models based on those parameters.

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Example Data

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